JXP9926SRG_E靖芯-恒佳盛原厂一级代理.pdf

靖芯 JXP9926SRG STBCHIP 20V Dual N-Channel Enhancement MOSFET DESCRIPTION SCHEMATIC DIAGRAM The JXP9926SRG uses advanced trench D1 D2 technology and design to provide excellent RDS(ON) with low gate charge. It can be used in a wide G1 G2 variety of applications. GENERAL FEATURES S1 S2  VDS =20V,ID =5.5A N1 N2 RDS(ON)=26mΩ (typical) @ VGS=4.5V PIN ASSIGNMENT RDS(ON)=37mΩ (typical) @ VGS=2.5V  High density cell design for ultra low Rdson SOP-8  Fully characterized avalanche voltage and Top View Bottom View current APPLICATION  Power switching application  Hard switched and high frequency circuits  Uninterruptible power supply PACKAGE XXYY: XX—years code，YY—weeks code  SOP-8 ORDERING INFORMATION Part Number Storage Temperature Package Marking Devices Per Reel JXP9926SRG -55°C to +150°C SOP-8 9926/XXYY 4000 ABSOLUTE MAXIMUM RATINGS (TA=25℃ unless otherwise noted) parameter symbol limit unit Drain-source voltage VDS 20 V Gate-source voltage VGS ±12 V T =25°C 5.5 Drain Current-Continuous (Silicon