集成电路封装和可靠性：芯片互连技术.pptxVIP

Chip Level Interconnection集成电路封装测试与可靠性芯片互连技术1 Wafer InWafer Grinding(WG研 磨 )Wafer Saw(WS 切 割 )Die Attach(DA 黏 晶 )Epoxy Curing (EC 银 胶 烘烤)Wire Bond (WB 引 线 键合)Die Coating (DC 晶 粒 封胶/涂覆)Molding(MD 塑 封 )Post Mold Cure (PMC 模 塑 后烘烤)Dejunk/Trim(DT 去 胶 去纬)Solder Plating (SP 锡 铅 电镀)Top Mark (TM 正 面 印码)Forming/Singular(FS 去 框 /成型)Lead Scan(LS 检 测 )Packing(PK 包 装 )典型的IC封装工艺流程集成电路封装测试与可靠性2 ??电子级硅所含的硅的纯度很高，可 达 99.9999 99999 %中德电子材料公司制作的晶棒(长度 达一公尺，重量超过一百公斤)集成电路封装测试与可靠性 3 集成电路封装测试与可靠性Wafer Back Grinding? PurposeThe wafer backgrind process reduces the thickness of the wafer produced by silicon fabrication (FAB) plant. The wash station integrated into the same machine is used to wash away debris left over from the grinding process.? Process Methods:1) Coarse grinding bymechanical. (粗磨)2) Fine polishing bymechanical or plasmaetching. (细磨抛光) 4 集成电路封装测试与可靠性下压力旋转及振荡轴在旋转平盘上之晶圆工作台仅在指示有晶圆期间才旋转? Method:The wafer is first mounted on a backgrind tape and is then loaded to the backgrind machine coarse wheel. As the coarse grinding is completed, the wafer is transferred to a fine wheel for polishing.5 集成电路封装测试与可靠性Wafer Back Grinding process1. Load and Align 3. Back grind Tape laminationObjective:To load and alignthe wafer into thewafer cleaning andtape laminationmachine.2. Wafer cleaningObjective:To clean the waferfor the nextlamination step.Objective:To laminate a protective layer of film on the circuitry surface of thewafer .4. Coarse grindingObjective:To reduce thethicknesswith a coarse grindingwheel.6 集成电路封装测试与可靠性Wafer Back Grinding process (Cont.)5. Fine polishing7. LoadObjective:To load thewafer to wafermounter.6. Unload8. Tape removalObjective:To unloadthe waferfrom backgrindingmachine.Objective:To remove theback grindtape afterwafer mountedon the frame.7 集成电路封装测试与可靠性Wafer Back Grinding Issues and Challenges? Issues? Ease of process–Thin wafer handling from one step to another–Back grinding tape removal–Excessive stresses removal or reduction from the wafer.（应力） ? Yield–Wafer breakage