先进FinFET工艺SoC全芯片aging 时序签核和电路EOS验证.pptxVIP

SOC Aging and EOS Solution SOC agingAging （HCI/BTI) will lead to timing violation afterfield application。LaunchFFClockCapture FFClockData Path(CombinationalLogic)Launch_clk_pathClock sourceCapture_clk_pathProcess VariationRC VariationVoltage Variation——no aging——aged5.00E-050.00E+001.50E-042.50E-042.00E-040.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8Idsat1.625X VDD DC Vgs=0.8V @125C 0s10000s 100000s 1.00E-04 550000s1000000s2? 2017 ANSYS, Inc.July 31, 2017ANSYS UGM 2017 SOC aging(a) Input Sp impact on cell delayAging library is not cover SP effect lead to 10% error.PinA1Pin A2Sp=0.5PinZnSp=13? 2017 ANSYS, Inc.July 31, 2017ANSYS UGM 2017(b) Delay degradation % due to aging on cells in a library with SP=0.1 and 0.9 SOC agingA new SOC Chip Level Aging Timing Sign-off Solution based on Ansys FXM and Path-FX? is introduced.Path-FX? is a path timing analysis tool that uses the FXM to perform fast SPICE-like simulation. It’s a Transistor level STA, so the variation of transistor can be involved in STA easily.CgdCgsCgbCsbCdbIdc (V, Pstat, Page)DSBGidG DS B4? 2017 ANSYS, Inc.July 31, 2017ANSYS UGM 2017 SOC agingCapture the pin SP of each cell by VCD or static method.Propagate the SP to each transistor in the cell.Calculate age_deltavth=F{ MTTF,Vgs,T,L ,sp,frequency, device type}SP: 0.25 Freq: 150MHzSP: 0.4 Freq: 100MHzSP: 0.8834 SP: 0.1167AB N1 YABN1 YSOC chipPIN5? 2017 ANSYS, Inc.July 31, 2017ANSYS UGM 2017 SOC agingThe solution has:1. Spice-like paths aging simulation2. Unique aging degradation for each device/cell which dependents on its workload in path;3. Fast runtimeNetlist（*.v）Parasitic Info.(SPEF File)SDCPathsLiberty? Modelsfor IP/IOReliabilityPDKStatic Timing Analysis Using FXMFXM withAgeFXMCharacterization(.DC Analysis)SPICEModelsStd. CellLPE NetlistTR/AFInformationFresh TimingReportAged TimingReportIs timing met？Aged Bottleneck AnalysisOptimizationSign off