基本逻辑电路设计.ppt

基本逻辑电路设计组合逻辑电路时序电路设计存储器组合逻辑电路设计简单门电路编、译码器与选择器加法器、求补器三态门及总线缓冲器简单门电路libraryIEEE;useIEEE.STD_LOGIC_1164.all;entitynand2is port( a:inSTD_LOGIC; b:inSTD_LOGIC; y:outSTD_LOGIC );endnand2;architecturenand2ofnand2isbeginy=anandb; endnand2;architecturenand2ofnand2isbegin process(a,b) variablecomb:std_logic_vector(1downto0); comb:=ab; casecombis when00=y=1; when01=y=1; when“10=y=1; when“11=y=0; whenothers=y=Z; endcase;endprocess;endnand2;或非门y=anorb;反相器y=nota;异或门y=axorb;编码器IF(d（0）＝‘0’）THENq=“11”;ELSIF(d(1)=‘0’)THENq=“10”;ELSIF(d(2)=‘0’)THENq=“01”;ELSEq=“00”;ENDIF;译码器CaseaisWhen“000”=q=;When“001”=q=;…..When“111”=q=;Whenorthers=q=“ZZZZZZZZ”;Endcase;ElseQ=“ZZZZZZZZ”;Endif;选择器ifsel=00then y=a;elsifsel=01then y=b;elsifsel=10then y=c;else y=d;endif;半加器libraryIEEE;useIEEE.STD_LOGIC_1164.all;entityhalf_adderis port( a:inSTD_LOGIC; b:inSTD_LOGIC; s:outSTD_LOGIC; co:outSTD_LOGIC );endhalf_adder;architecturehalf_adderofhalf_adderissignalc,d:std_logic;beginc=aorb;d=anandb;co=notd;s=candd;endhalf_adder;全加器libraryIEEE;useIEEE.STD_LOGIC_1164.all;entityfull_adderis port( a,b,cin:inSTD_LOGIC; co,s:outSTD_LOGIC);endfull_adder;architecturefull_adderoffull_adderiscomponenthalf_adder port( a,b:inSTD_LOGIC; s,co:outSTD_LOGIC);endcomponent;signalu0_co,u0_s,u1_co:std_logic;beginu0:half_adderportmap(a,b,u0_s,u0_co);u1:half_adderportmap(u0_s,b,cin,s,u1_co);co=u0_cooru1_co;endfull_adder;三态门ifen=1then dout=din;else dout=Z;endif;单向总线缓冲器ifen=1then dout=din;else dout=“ZZZZZZZZ”;endif;双向缓冲器process(a,dr,en)beginifen=0anddr=1then bout=a;else bout=ZZ