等精度频率计设计VHDL程序.docVIP

FreqtestSimple.vhd

Project:

1

2--Filename:

3--

testbench.vhd

4--Description:

5--

6--

testbenchmodule

7--Copyright(c)2005byJohnYuan

8--

9--

AnX.M.U.T.Projects

freetouse,butseedocumentationforconditions

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--Revision

--Revision

--

--1.0

--

--

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityyuanis

History:

Date

Nev.6th2006

Author

YichaoChen;ShiqinHuang

Comment

Initialrevision

port(bclk:instd_logic;--Systemclk50MHz

tclk:instd_logic;--Pulseundermeasure

clr

cl

:instd_logic;--Resetsignal

:instd_logic;--MCUtestcommandinput

start:outstd_logic;--Measurestartandstopsignal

:instd_logic_vector(2downto0);--Dataoutputselect

data:outstd_logic_vector(7downto0));--OutputdatatoMCU

endyuan;

sel

architectureoneofyuanis

signalbzq,tsq:std_logic_vector(31downto0);

signalena:std_logic;

begin

--signalenaequalstostart

start=ena;--

--Dataselectioncommand,MCUreaddatafromCPLD

data=bzq(7downto0)

bzq(15downto8)

bzq(23downto16)whensel=010else

bzq(31downto24)whensel=011else

tsq(7downto0)

tsq(15downto8)

tsq(23downto16)whensel=110else

tsq(31downto24)whensel=111else

tsq(31downto24);

--Dff

d:process(tclk,clr,cl)

begin

ifclr=1thenena=0after1ns;

elsiftclkeventandtclk=1thenena=clafter1ns;

endif;

endprocess;

--Measuringcounter,clockedbypulseundermeasure

tf:process(tclk,clr,ena)--

begin

ifclr=1thentsq=(others=0)after1ns;

elsiftclkeventandtclk=1then

ifena=1thentsq=tsq+1after1ns;

endif;

endif;

endprocess;

whensel=000else

whensel=001else

whensel=100else

whensel=101else

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FreqtestSimple