VerilogHDL行为语句公开课一等奖课件省赛课获奖课件.pptx

VerilogHDL行为语句电子信息通信学科

27VerilogHDL行为语句类别语句可综合性过程语句InitialalwaysOK块语句串行块begin-endOK并行块fork-join赋值语句持续赋值assignOK过程赋值=，=OK条件语句If-elseOKcaseOK循环语句forOKrepeatwhileforever编译指示语句‘defineOK‘includeOK‘ifdef,’else,’endifOK

3initialalways7.1过程语句

4always@(event-expression)begin//过程赋值//if-else,case,casex,casez选择语句//while,repeat,for循环//task,function调用end7.1always过程语句

5@(a)//当信号a的值发生变化@(aorb)//当信号a或信号b的值发生变化@(posedgeclk)//当clk的上升沿到来时@(negedgeclk)//当clk的下降沿到来时@(posedgeclkornegedgereset)@(negedgeclkorposedgereset)7.1event-expression

6modulemux4_1(in0,in1,in2,in3,sel,out);inputin0,in1,in2,in3;input[1:0]sel;outputout;regout;always@(in0orin1orin2orin3orsel)case(sel)2’b00:out=in0;2’b01:out=in1;2’b10:out=in2;2’b11:out=in3;default:out=2’bx;endcaseendmodule7.1例7.1

7modulecount(clk,reset,load,data,out);inputclk;inputreset;inputload;input[7:0]data;output[7:0]out;reg[7:0]out;always@(posedgeclk)beginif(!reset)out=8h00;elseif(load)out=data;elseout=out+1b1;endendmodule7.1posedgenegedge

8always@(posedgeclk)beginif(!reset)out=8h00;elseif(load)out=data;elseout=out+1b1;end7.1posedgenegedge

9always@(negedgeclk)beginif(!reset)out=8h00;elseif(load)out=data;elseout=out+1b1;end7.1posedgenegedge

10moduleaaa(clk,clear,in,out);inputclk;inputclear;input[7:0]in;output[7:0]out;reg[7:0]out;always@(posedgeclkorposedgeclear)beginif(clear)out=8b0;elseout=in;endendmodule7.1posedgenegedge

11modulecnt(CLK,RST,Q);inputCLK,RST;output[1:0]Q;reg[1:0]Q;always@(posedgeCLKornegedgeRST)if