超大CMOS集成电路原理chapter4.pptx

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1DigitalIntegratedCircuits

ADesignPerspectiveTheWireJanM.RabaeyAnanthaChandrakasanBorivojeNikolic

2TheWireschematicsphysical

3InterconnectImpactonChip

4WireModelsAll-inclusivemodelCapacitance-only

5ImpactofInterconnectParasiticsInterconnectparasiticsreducereliabilityaffectperformanceandpowerconsumptionClassesofparasiticsCapacitiveResistiveInductive

6NatureofInterconnectGlobalInterconnectSLocal=STechnologySGlobal=SDieSource:Intel

7INTERCONNECTCapacitance

8CapacitanceofWireInterconnect

9Capacitance:TheParallelPlateModel

10Permittivity

11FringingCapacitance

12FringingversusParallelPlate

13InterwireCapacitance

14ImpactofInterwireCapacitance

15WiringCapacitances(0.25mmCMOS)

16INTERCONNECTResistance

17WireResistance

18InterconnectResistance

19DealingwithResistanceSelectiveTechnologyScalingUseBetterInterconnectMaterialsreduceaveragewire-lengthe.g.copper,silicidesMoreInterconnectLayersreduceaveragewire-length

20PolycideGateMOSFETn+n+SiO2PolySiliconSilicidepSilicides:WSi2,TiSi2,PtSi2andTaSiConductivity:8-10timesbetterthanPoly

21SheetResistance

22ModernInterconnect

23Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric

24INTERCONNECTInductance

25InterconnectModeling

26TheLumpedModel

27TheLumpedRC-Model

TheElmoreDelay

28TheEllmoreDelay

RCChain

29WireModelAssume:WiremodeledbyNequal-lengthsegmentsForlargevaluesofN:

30TheDistributedRC-lineThediffusionequation

31Step-responseofRCwireasafunctionoftimeandspace

32RC-Models

33DrivinganRC-line

34DesignRulesofThumbrcdelaysshouldonlybeconsideredwhentpRCtpgateofthedrivinggateLcrit?tpgate/0.38rcrcdelaysshouldonlybeconsideredwhentherise(fall)timeatthelineinputissmallerthanRC,therise(fall)timeofthelinetriseRCwhennotmet,thechangeinthesignalisslowerthanthepropagationdelayofthewire?MJIrwin,PSU,2023

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