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FinalExamProject4bitFullAdderLayoutandAnalysisusingLasiandWinSpice

AssignmentObjectivesDoahierarchallayoutofahalfadder,fulladderand4bitadderusingLASI,thensimulatethecircuitusingSPICEtomakesurethatthedesignwillwork.

OverviewHierarchalLayoutdesignisdoneusingLasi.N3X2,P3X2,NAND,XOR,Half-Adder,Full-Adderand4bitFullAdderlayoutsaremadeinhierarchalsfashionusingbottomupapproach.EachCellisanalyzedbyusingWinspice3.CIRfilecreatedbyLasi.

P3X2(Rank1)Cell-StandardcellfromLasiLibrary

N3X2(Rank2)Cell-StandardcellfromLasiLibrary

INVERTER(Cont’d)InvertercellhasRank2.InvertercellismadeusingP3X2andN3X2cell.ItisusedtoprovideA’andB’forXORinputandNANDinputtomakeORgate.AlsoitisusedatoutputofaNANDtomakeAND.

INVERTER

NAND(Cont’d)NANDcellhasrank2.ItisusedtomakeANDgateandORgate.

NAND

XOR(Cont’d)XORcellhasRank2.ItisismadetoprovidesumofHalfAdder.ItislittledifferentthanregularXORbecauseitrequiresfourinputsA,A’,B,andB’.Bydesigninginwithfourinputswesimplifydesignandreducedtransistors.

XOR

Half-Adder(Cont’d)Half-Adderhasrank3.ItisdesignedusingINVERTER,NANDandXORgate.Sum=AB’+B’A.Carry=AB.

Half-Adder

Full-Adder(Cont’d)Ithasrank4.FulladderismadeusingtwoHALF-ADDER,2InverterandaNANDgate.S1=HA(A,B)Sum=HA(S1,CarryIn)Carry=OR(Carry1,Carry2)

Full-Adder

4BitFullAdder(Cont’d)Ithasrank5.Itismadeusingfour1bitFull-Adder.FirstFull-AdderhasCarryin0.4thCarryoutisFinalCarryoutof4bitFull-Adder.

4BitFullAdder

SPICESIMULATIONEachcelliscompiledusingLasiCkt.Generate.CIRfilesusedinWinSpice3forsimulationofcircuit.Everyanalyzedsignalisoffsetby6Vtoseeeachsignalproperly.

INVERTERSimulation(Cont’d)NextslideshowsscreencaptureofInvertersimulation.A_isoutputofsignalinputsignalA.

INVERTERSimulation

NANDS