用verilog写正弦波发生器.docx

modulesin(clk,rst_n,clock_1,addr_div_1,sin_data);

modulesin(clk,rst_n,clock_1,addr_div_1,sin_data);

inputclk;

inputclk;

inputclk;inputrst_n;

output[9:0]sin_data;output[9:0]addr_div_1;

//output[9:0]addr_div;outputclock_1;

wireclock;wire[9:0]addr_div;wire[9:0]address;wire[9:0]line;

//wire[7:0]q;

//wire[9:0]cnt_temp;

divU1(

.clk(clk),

.rst_n(rst_n),

.clock_1(clock_1),

.clock(clock)

);

counterU2(

.clock(clock),

.rst_n(rst_n),

.addr_div_1(addr_div_1),

.addr_div(line)

);

sinwave U3(

.clock(clock),

.address(line),

.q(sin_data)

);

endmodule

modulediv(clk,rst_n,clock,clock_1);

inputrst_n;

inputrst_n;

always@(posedgeclockornegedgerst_n)

always@(posedgeclockornegedgerst_n)

outputclock;outputclock_1;

reg[9:0]count;reg[9:0]count_temp;

always@(posedgeclkornegedgerst_n)begin

if(!rst_n)

begin

count=10d0;count_temp=0;end

elseif(count==10d24)begin

count=10d0;

count_temp=~count_temp;end

elsebegin

count=count+10d1;end

end

wireclock,clock_1;

assignclock=count_temp;assignclock_1=count_temp;

endmodule

modulecounter(clock,rst_n,addr_div,addr_div_1);inputclock;

inputrst_n;

output[9:0]addr_div;output[9:0]addr_div_1;

reg[9:0]cnt;reg[9:0]cnt_temp;

if(!rst_n)

if(!rst_n)

13:552;

13

:

552;

cnt=10d0;

elseif(cnt==10d1023)cnt=10d0;else

cnt=cnt+10d1;

always@(posedgeclockornegedgerst_n)if(!rst_n)

cnt_temp=10d0;

elseif(cnt==10d1023)cnt_temp=10d0;

else

cnt_temp=cnt;

wire[9:0]addr_div,addr_div_1;assignaddr_div=cnt_temp;assignaddr_div_1=cnt_temp;

endmodule

//正弦波形数据，做ROM用

WIDTH=10;

DEPTH=1024;

ADDRESS_RADIX=UNS;

DATA_RADIX=UNS;

CONTENTBEGIN

0 : 511;

1 : 514;

2 : 517;

3 : 520;

4 : 524;

5 : 527;

6 : 530;

7 : 533;

8 : 536;

9 : 539;

10 : 542;

11 : 545;

12 : 549;

14:555;

14

:

555;

57:686;

57

:

686;

15 : 558;

16 : 561;

17 : 564;

18 : 567;

19 : 570;

20 : 574;

21 : 577;

22 : 580;

23 : 583;

24 : 586;

25 : 589;

26 : 592;

27 : 595;

28 : 598;

29 : 602;

30 : 605;

31 : 608;

32 : 611;

33 : 614;

34 :