8位十进制频率计.pdf

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYCNT10IS

PORT(CLK:INSTD_LOGIC;

CLR:INSTD_LOGIC;

ENA:INSTD_LOGIC;

CQ:OUTINTEGERRANGE0TO15;

CARRY_OUT:OUTSTD_LOGIC);

ENDCNT10;

ARCHITECTUREbehavOFCNT10IS

SIGNALCQI:INTEGERRANGE0TO15;

BEGIN

PROCESS(CLK,CLR,ENA)

BEGIN

IFCLR=1THENCQI=0;

ELSIFCLKEVENTANDCLK=1THEN

IFENA=1THEN

IFCQI9THENCQI=CQI+1;

ELSECQI=0;

ENDIF;

ENDIF;

ENDIF;

ENDPROCESS;

PROCESS(CQI)

BEGIN

IFCQI=9THENCARRY_OUT=1;

ELSECARRY_OUT=0;

ENDIF;

ENDPROCESS;

CQ=CQI;

ENDbehav;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYREG32BIS

PORT(Load:INSTD_LOGIC;

DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);

DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));

ENDREG32B;

ARCHITECTUREbehavOFREG32BIS

BEGIN

PROCESS(Load,DIN)

BEGIN

IFLoadEVENTANDLoad=1THENDOUT=DIN;

ENDIF;

ENDPROCESS;

ENDbehav;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYTESTCTLIS

PORT(CLK:INSTD_LOGIC;

TSTEN:OUTSTD_LOGIC;

CLR_CNT:OUTSTD_LOGIC;

load:OUTSTD_LOGIC);

ENDTESTCTL;

ARCHITECTUREbehavOFTESTCTLIS

SIGNALDiv2CLK:STD_LOGIC;

BEGIN

PROCESS(CLK)

BEGIN

IFCLKEVENTANDCLK=1THEN

Div2CLK=NOTDiv2CLK;

ENDIF;

ENDPROCESS;

PROCESS(CLK,Div2CLK)

BEGIN

IFCLK=0ANDDiv2CLK=0THENCLR_CNT=1;

ELSECLR_CNT=0;ENDIF;

ENDPROCESS;

Load=NOTDiv2CLK;TSTEN=Div2CLK;

ENDbehav;

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYFREQTESTIS