verilog-32位浮点加法器程序及代码解释.pdfVIP

verilog-32位浮点加法器程序及代码解释

moduleflowadd(ix,iy,clk,a_en,ost,oz);

inputix,iy,clk,a_en;

outputoz,ost;

wire[31:0]ix,iy;

reg[31:0]oz;

wireclk,ost,a_en;

reg[25:0]xm,ym,zm;

reg[7:0]xe,ye,ze;

reg[2:0]state;

parameter

start=3b000,zerock=3b001,exequal=3b010,addm=3b011,infifl

=3b100,over=3b110;

assignost=(state==over)?1:0;/*后端处理，输出浮点数*/

always@(posedgeost)

begin

if(a_en)

oz={zm[25],ze[7:0],zm[22:0]};

end

always@(posedgeclk)//状态机

begin

case(state)

start://前端处理，分离尾数和指数，同时还原尾数

begin

xe=ix[30:23];

xm={ix[31],1b0,1b1,ix[22:0]};

ye=iy[30:23];

ym={iy[31],1b0,1b1,iy[22:0]};

state=zerock;

end

zerock:

begin

if(ix==0)

begin

{ze,zm}={ye,ym};

state=over;

end

else

if(iy==0)

begin

{ze,zm}={xe,xm};

state=over;

end

else

state=exequal;

end

exequal://指数处理，使得指数相等

begin

if(xe==ye)

state=addm;

else

if(xeye)

begin

ye=ye+1;

ym[24:0]={1b0,ym[24:1]};

if(ym==0)

begin

zm=xm;

ze=xe;

state=over;

end

else

state=exequal;

end

else

begin

xe=xe+1;

xm[24:0]={1b0,xm[24:1]};

if(xm==0)

begin

zm=ym;

ze=ye;

state=over;

end

else

state=exequal;

end

end

addm://带符号位和保留进位的尾数相加

begin

if((xm[25]^ym[25])==0)

begin

zm[25]=xm[25];

zm[24:0]=xm[24:0]+ym[24:0];

end

else

if(xm[24:0]ym[24:0])

begin

zm[25]=xm[25];

zm[24:0]=xm[24:0]-ym[24:0];

end

else

begin

zm[25]=ym[25];

zm[24:0]=ym[24:0]-xm[24:0];

end

ze=xe;

state=infifl;

end

infifl://尾数规格化处理

begin

if(zm[24]==1)

begin

zm[24:0]={1b0,zm[24:1]};

ze=ze+1;

state=over;

end

else

if(zm[23]==0)

begin

zm[24:0]={zm[23:0],1b0};

ze=ze-1;

state=infifl;

end

else

state=over;

end

over:

begin

state=st

art;

end

default:

begin

state=sta