数字设计课件第6章组合逻辑设计实践.pptVIP

2025/4/61Chapter6CombinationalLogicDesignPracticesMSIbuildingblocksaretheimportantelementofcombinationalcircuits.

本章重点2025/4/62chapter6具备一定功能的通用组合逻辑电路的设计方法及实例掌握常用的MSI的使用方法及功能扩展掌握译码器、MUX实现组合逻辑功能的方法能分析、设计由MSI构建的电路

2025/4/6chapter636.1DocumentationStandard1.SignalNamesandActiveLevelsMostsignals(signalname)haveactivelevel.activehighactivelowNamingconventionsurffix“_L”attachingtosignalnamerepresentactivelowlevel.Like,EN_L、READY_L……Inlogicrelation,EN_L=EN’，READY_L=READY’。

2025/4/6chapter642.ActivelevelsforpinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversionbubbleActivelowENENDinstartDoutflgstartDinDoutflgActivehign

2025/4/6chapter65Exp2：①EN=1(activehigh),datacanbetransferred②EN=0(activelow),datacanbetransferredENCLKEN_LCLK

2025/4/6chapter663.bubble-to-bubblelogicdesignMakethelogiccircuiteasiertounderstand.Exp：NotmatchABSELDATAABASELDATAmatch

chapter66.3CombinationalPLDsProgrammablelogicarrays(PLA)twolevel“AND—OR”device.Canbeprogrammedtorealizeanysum-of-productslogicexpression.Ann×mPLAwithpproductterms:n—inputsm—outputsp—productterms

01chapter603ANDarray024×3with6productterms04ORarray

chapter6

chapter62.ProgrammableArrayLogicDevicesFixedORarray，programmableANDarrayBidirectionalinput/outputpins，熔丝型PAL16L8，Outputenable

chapter63.GenericArrayLogicDevices（GAL）aninnovationofthePAL;canbeerasedandreprogrammed;

6.4Decoder2025/4/6chapter612Animportanttypeofcombinationalcircuit.inputcodeword

enableinputOutputcodeword

decodeer1-to-1mapping1-out-of-mcodenmn-bitm-bit

1、bianrydecoders2025/4/6chapter613inputcode：n-bitoutputcode：2n-bit⑴2-4decoder（2-22）I1I0Y3Y2Y1Y0truthtable：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=miY0=I1’·I0’ Y1=I1’·I0Y2=I1·I0’ Y3=I1·I02-4decoderOneinputcombinationchoosesanoutputport.

2025/4/6chapter6142-4decoderwithenableinputYi=EN·miENI1I0Y3Y2Y1Y00××00001000001101001011001