数字信号处理dsp教学课件单元六.pptVIP

6-*6-*单元6:C28x模数转换器32-Bit-DigitalSignalControllerTMS320F2812ADC模块12-bit精度ADC16个模拟输入脚(0to3V)两个模拟输入选择器最多8个模拟输入每通道两个采样/保持单元序列和同步采样模式自动序列容量–最多可达16个自动转换两个独立的8状态序列发生器“双序列发生器模式”“级联模式”16个可个别寻址的结果寄存器多触发源启动转换外部触发,软件触发,事件管理器事件ADCModuleBlockDiagram(级联模式)12-bitA/DConverterResultSelectResultMUXRESULT0...RESULT1RESULT2RESULT15CHSEL00(state0)CHSEL01(state1)CHSEL02(state2)CHSEL03(state3)CHSEL15(state15)...MAX_CONV1AutosequencerStartSequenceTriggerSOCEOCSoftwareEVAEVBExtPin(ADCSOC)AnalogMUXMUXAADCINA0ADCINA1ADCINA7...MUXBADCINB0ADCINB1ADCINB7...S/HAS/HMUXS/HBADCModuleBlockDiagram(双序列发生器模式)12-bitA/DConverterSoftwareEVAExtPin(ADCSOC)ResultSelectResultMUXRESULT0...RESULT1RESULT7ResultSelectRESULT8...RESULT9RESULT15CHSEL00(state0)CHSEL01(state1)CHSEL02(state2)CHSEL07(state7)...MAX_CONV1AutosequencerStartSequenceTriggerSOC1/EOC1SEQ1CHSEL08(state8)CHSEL09(state9)CHSEL10(state10)CHSEL15(state15)...MAX_CONV2AutosequencerStartSequenceTriggerSEQ2SequencerArbiterSOC2/EOC2SoftwareEVBAnalogMUXMUXAADCINA0ADCINA1ADCINA7...MUXBADCINB0ADCINB1ADCINB7...S/HAS/HMUXS/HBF2812ADCClockingExampleCLKIN(30MHz)HSPCLK(150MHz)ADCCLKPSbitsADCTRL30011bFCLK(25MHz)FCLK=HSPCLK/(2*ADCCLKPS)ADCCLK=FCLK/(CPS+1)ADCCLK(25MHz)CPSbitADCTRL10bToADCpipelinesamplingwindowACQ_PSbitsADCTRL10111bImportant:ADCCLK最大可达25MHz!SYSCLKOUT(150MHz)PLLCRDIVbits1010bToCPUsamplingwindow=(ACQ_PS+1)*(1/ADCCLK)PCLKCR.ADCENCLK=1HISPCPHSPCLKbits000bAnalog-to-DigitalConverterRegisters

ADCTRL1 0x007100ADCControlRegister1ADCTRL2 0x007101ADCControlRegister2ADCMAXCONV0x007102ADCMaximumConversionChannelsRegisterADCCHSELSEQ10x007103ADCChannelSelectSequencingControlRegister1ADCCHSELSEQ20x007104A